1. Field of the Invention
The present invention relates to a data transfer device, a method of transferring data, and an image forming apparatus that control data transfer that is performed by a plurality of direct memory access controllers (DMACs) through one bus.
2. Description of the Related Art
In a case where a large-scale integration (LSI) includes a plurality of DMACs therein and the plurality of DMACs accesses one bus, generally, an arbitrating mechanism (arbiter) for the DMACs is arranged inside the LSI so as to improve transfer performance of the LSI. In addition, it is usual to provide the arbiter with a mechanism which assures performance by setting a high priority on acceptance of a request from a DMAC that is responsible for data transfer such as video transfer for which time limitation is strict and setting a relatively low priority on acceptance of a request from a DMAC that is responsible for data transfer to perform a process such as a compression/decompression process or a rotation process, for which time limitation is not strict and which is performed in parallel with a video transfer process.
A data transfer process using a plurality of DMACs having different priorities will be briefly described with reference to FIG. 18. As illustrated in FIG. 18, a controller LSI 300 and a central processing unit (CPU) 302 are interconnected through a bus 301 that is, for example, compliant with peripheral component interconnect bus express (PCI Express) specifications, and the CPU 302 and a memory 304 are interconnected through a bus 303. The PCI Express specifications support split transaction in which a request and a response are separately processed, and accordingly, a next request can be issued without waiting for a response for a previous request.
The controller LSI 300 includes a plurality of DMACs 310a, 310b, 310c and 310d having different priorities. In addition, the controller LSI 300 includes: an arbiter 311 that arbitrates data transfer of the plurality of DMACs 310a to 310d; a PCIe I/F 312 that is an interface for the bus 301; and a transmission data buffer 313 that performs buffering of transfer data.
For example, in the controller LSI 300, the arbiter 311 arbitrates read requests to the memory 304 that are transmitted from the DMACs 310a to 310d based on the priorities to transmit the read requests to the CPU 302 through the bus 301. The CPU 302 reads out data from the memory 304 through the bus 303 in response to the requests and transmits the read-out data to the controller LSI 300 through the bus 301.
In order to support the split transaction, the plurality of DMACs 310a to 310d can respectively issue a request without waiting for a response. When read data is normally transferred, as illustrated in FIG. 18 as an example, the DMACs 310a to 310d can issue their respective read requests 320a to 320d for reading out read data 330a to 330d from the memory 304 without waiting for the responses of the read data 330a to 330d. Accordingly, the transfer through the bus 301 can be efficiently performed.
In addition, Japanese Patent Application Laid-open No. 2003-256359 discloses a technique in which a direct memory access (DMA) arbitrating mechanism based on priorities is provided, and in a case where a request for starting DMA transfer is received while another DMAC is operating, if the priority of the requested DMA transfer is higher than that of the DMAC, a channel to be disengaged is selected in accordance with content of a process of the transfer and the priority of the DMAC that is in the middle of operation.
However, in a conventional arbiter mechanism, it is not rare that a request from a DMAC having a high priority, is not allowed to be received for a long time, which makes it difficult to satisfy a limitation of data transfer time, resulting in an abnormality occurring in the data transfer. Such an abnormality in the data transfer appears as an image abnormality in a case where the transfer data is image data, for example.
The data transfer resulting in an abnormal image being generated will be briefly described with reference to FIG. 19. In the above-described split transaction, there is an upper limit of number of requests, which can be issued without waiting for a response, due to practical restriction when implementing a circuit. Accordingly, in a state in which current number of requests, which has been issued and a response to which has not been received, reaches an upper limit, the DMACs 310a to 310d are not allowed to issue a new request to the arbiter 311 until a transaction started from the request that is currently waiting for a response is completed.
Accordingly, an abnormal image is generated in a case where the following conditions (1) and (2) are satisfied together.
Condition (1): A state is reached in which a DMAC having a high priority among the DMACs 310a to 310d, is not allowed to issue a new read request.
Condition (2): A size of data to be transferred according to a write request issued by a DMAC having a low priority among the DMACs 310a to 310d is large, or there are a plurality of write requests issued by a DMAC having a low priority.
Referring to FIG. 19, it is assumed that the number of the requests, which has been issued and a response to which has not been received, reaches the upper limit at a time point when the DMAC (here, the DMAC 310a) having a high priority issues a read request 340a, and a state is reached in which the DMAC 310a is not allowed to issue a new read request, whereby Condition (1) is satisfied. By receiving a response to the read request 340a, the DMAC 310a can issue the next read request.
In addition, it is assumed that, in the state in which the DMAC 310a having a high priority is not allowed to issue a new read request, a write request 341 made by a DMAC (here, a DMAC 310b) having a low priority is allowed by the arbiter 311. The write request 341 causes transfer of write data packet that includes write data to be written into the memory 304. Since a size of data to be transferred as a write request is generally larger than a size of data to be transferred as a read request, in a case where a size of the write data included in a write request packet is large, Condition (2) is satisfied.
When a response (read data 342a) to the read request 340a made by the DMAC 310a having a high priority is received by the DMAC 310a after Conditions (1) and (2) are satisfied as above, a state is reached in which the DMAC 310a can issue a next read request 340b, and issuance of the read request 340b is allowed by the arbiter 311. Meanwhile, a write request 341 made by the DMAC 310b having a low priority is accepted by the arbiter 311, before the read request 340b is issued. Accordingly, the read request 340b is transmitted after completion of transmission of the write request 341.
When once such a state is reached, the same sequence is repeated any number of times as long as the write request is continuously repeated from the DMAC 310b. As a result, data transfer performance for a read request made by the DMAC 310b having a high priority is degraded, and a limitation on data transfer time may not be satisfied. For example, in a case where continuity between the read data 342a responding to the read request 340a issued first by the DMAC 310a and read data 342b responding to the read request 340b issued next is required, the required continuity between the read data 342a and the read data 342b may not be obtained. Such a problem may occur in a case of a technique disclosed in Japanese Patent Application Laid-open No. 2003-256359 described above as well.